On-chip Self Testing using BIST-oriented Random Access Memory

The increased circuit density in today’s integrated circuits demands for efficient and low cost testing as compared to the testing of logic with external test equipment. The Built-In Self Test (BIST) architecture provides the self-testing of logic circuit but is not at the positive extreme in delivering deterministic and limited test vectors and storage and compression of output test responses. On-chip Self Testing using BIST-oriented Random Access memory employs a new logic BIST methodology that can deliver deterministic test vectors and stores the compacted of output responses in the memory. The circuit is tested with the predetermined test-vectors and the output responses are compacted and then compared with the original error-free values to detect the presence of faults, if any. The proposed scheme being presented in this paper consists of test data compression logic and onchip SRAM structure, which acts as a ROM when the test mode is on. The new BIST oriented SRAM (BRAM) implements ROM features in the test mode and incurs no penalty in the normal SRAM mode of operation. BRAM can be designed by adding extra word line in a row to a SRAM cell. It stores the compressed test vectors that can be given to on-chip de-compressors during test mode. The de-compressor decompresses the compacted test data and gives to the CUT and the responses are compacted using a compactor circuit and this compacted response is compared with the original error free responses in a comparator circuit to detect the faults.